It may be necessary in several signal processing applications to generate a digital product formed by multiplying a digital operand with a digital word, wherein the digital word is indicative of an analog input. It may also be necessary to manipulate the digital word together with the digital product in subsequent processing steps, which may include a frequency domain transformation. A conventional approach for generating both the digital word and the digital product is to first convert the analog input to the digital word representative thereof by employing a conventional analog/digital converter (ADC). A conventional digital multiplier may subsequently generate the digital product by multiplying the digital operand and the digital word. As a consequence of performing the multiplication subsequent to the completion of the conversion, this conventional approach is inherently slow and therefore may be undesirable.
In U.S. Pat. No. 3,470,363 issued Sep. 30, 1969 titled “Hybrid Multiplier Apparatus”, Aitchison discloses a circuit arrangement for generating the digital product by multiplying the digital operand directly with the analog input. Particularly, the hybrid multiplier generates the digital product of a desired precision by successively generating trial digital products, dividing each trial digital product by the analog input to form a quotient, and comparing each quotient to the digital word. Since the precision for the digital product is commonly determined by combining the word lengths of the two operands as per conventional multipliers, the number of trial products, and accordingly, the number of clock cycles associated with making available the digital product may become unnecessarily excessive.
In U.S. Pat. No. 4,291,387 issued Sep. 22, 1981 titled “Analog to Digital Conversion Weighting Apparatus”, Buchanan et al. disclose a circuit arrangement for generating the digital product formed by multiplying the digital operand with the digital word. The apparatus includes control means configured to transfer, from a bucket-brigade sequential ADC to a traditional sequential multiplier, each resolved bit of the digital word in succession from the most significant bit to the least significant bit. During a given conversion cycle, the sequential ADC outputs a resolved bit of the digital word and the control means transfers the resolved bit to the sequential multiplier where a partial product is generated in response to the resolved bit and the digital operand prior to the end of the conversion cycle, wherein a substantial portion of the conversion cycle is dedicated to generating the resolved bit. The partial product is then temporarily latched or stored for use in the following conversion cycle. During the next conversion cycle, as the sequential ADC outputs the next resolved bit of the digital word and the control means transfers the next resolved bit to the sequential multiplier for partial product generation, the sequential multiplier adds to a weighted summation of partial products the partial product generated in the previous conversion cycle.
Although the apparatus of Buchanan et al. sequentially processes the digital product and the digital word concurrently, according to Buchanan et al., the sequential multiplier makes available the digital product “substantially adjacent to the time of conversion of the least significant bit” of the digital word since the sequential multiplier temporarily latches or stores partial products. Particularly, the availability of the digital product lags the availability of the digital word by one conversion cycle such that the overall cycle latency of the apparatus for making available both the digital word and the digital product is one more than the number of cycles consumed by the sequential converter for converting the analog input.
In light of the aforementioned limitations and noting that it may be necessary to manipulate the digital word together with the digital product in subsequent processing steps, it is believed that a need remains for providing an apparatus which can substantially maintain the operative frequency at which the digital word is sequentially processed yet reduce the cycle latency associated with making available the digital product relative to the digital word.